1. Field of the Invention
The present invention relates generally to phase-lock loop systems, and more specifically, to a method and system for canceling jitter in fractional-N phase lock loop circuits.
2. Background of the Invention
Phase-lock loop (PLL) circuits are used abundantly in audio and video processing systems, communications systems and in other systems such as processing systems where generation of a clock having a selectable or synchronized frequency is required. In many applications, it is desirable to generate a selectable frequency other than a simple multiple or division of a reference clock frequency. Circuits such as synthesizers provide a programmable frequency from a reference using a PLL.
In order to control the frequency of an oscillator in small frequency increments using a PLL, in the past it was necessary to generate a much higher output frequency than the desired output frequency. The PLL output frequency was controlled by dividing the generated frequency by one numeric value and comparing its phase to a reference frequency that was divided by another numeric value. The resultant output frequency after division was determined by the ratio of the two divisors in the above operations and the system provided thereby is known as a ratiometric synthesizer and the frequency provided thereby has a rational relationship to the reference frequency. However, in order to provide a frequency selectivity on the order of 1 percent, the oscillator output frequency and reference frequency typically needed to be 100 times greater than the desired output frequency.
More recently, fractional-N PLLs have been developed that can provide a rationally related frequency from a reference without requiring generation of a high output frequency from the oscillator. Fractional-N PLLs provide a rational frequency control relationship by providing a “rational frequency divider” operation that approximates a rational division over the long-term by generating pulses that do not conform to a simple integer division of the oscillator output. As long as the PLL loop time constant is low compared to any beat frequencies that would otherwise be generated in the loop, the output frequency of the PLL's oscillator can be set to a rational multiple of the reference clock frequency. However, the rational frequency divider operation generally either requires a very low loop bandwidth in order to filter the dithering noise generated by the rational approximation, or the noise must somehow be shaped to fall outside of the filter bandwidth.
One technique that has been applied in fractional-N PLL circuits is to use a delta-sigma modulator to shape the noise spectrum introduced by the rational frequency division pulses, by generating pulses that have a noise spectrum that falls outside of the loop bandwidth, such as the PLL disclosed in U.S. Pat. No. 5,825,253, the specification of which is incorporated herein by reference. Although it is the reference clock that is rationally divided in the above-incorporated patent, the rational frequency division can be applied at either input to the phase comparator. Such techniques permit a much wider loop bandwidth for the PLL and thus a faster lock time and wider capture range.
The delta-sigma modulator approach provides a stable PLL that is rationally programmable over a wide range of frequency values. However, there is typically a significant residual amount of jitter (phase noise) present that is within the bandwidth of the loop.
Another example of fractional-N PLL jitter reduction through noise shaping is disclosed in U.S. Patent Application Publication No. US20050169419A1 by the inventor of the present application and assigned to the same assignee, and which is incorporated herein by reference. The above-incorporated U.S. patent application discloses a delta-sigma modulator used to generate a rational division in the PLL feedback look and using an improved phase-frequency detector that shapes the output noise spectrum by increasing the effective resolution of the digital phase comparator.
Another technique that has been applied to reduce jitter in a delta-sigma modulator driven fractional-N PLL is to introduce a correction signal that directly calculates the delta-sigma quantization error that is observed between the input and the output of the modulator and applies a correction voltage to the loop filter and thus the oscillator. The effect of the correction signal is to directly remove jitter (phase noise) due to the quantization error in the modulator. However, the entire cancellation signal path must be highly linear in order not only to achieve cancellation of the jitter but also to ensure that additional artifacts are not added within the loop bandwidth of the PLL.
Therefore, it would be desirable to provide a method and apparatus for canceling jitter in a fractional-N PLL that reduces jitter (phase noise) in the output of the PLL with low sensitivity to non-linearities in the cancellation circuit. It would further be desirable to accomplish such cancellation without requiring much additional circuitry for implementation.